1. Field of the Disclosure
The present disclosure relates to liquid crystal displays, and in particular relates to array substrates and methods for manufacturing the same.
2. Description of the Related Art
In LCD manufacturing, the efficiency of the backlight and display brightness is directly influenced by the aspect ratio of pixel devices. A major factor of the aspect ratio is the distance between the data line and the transparent conductive electrode. If the distance therebetween is too short, the capacitance between the pixel and the data line (Cpd) is higher. In such a case, the full charged pixel electrode will change before a next signal transfer due to different voltages from the data line.
To reduce Cpd effect, a high aspect ratio structure is used, as shown in FIG. 1A, wherein a shielding electrode is disposed between the data line and the pixel electrode, wherein the shielding electrode is electrically connected to a common potential. Because the shielding electrode shields the electrical field of the data line, the pixel electrode is free from the influence of the data line signal, thereby reducing the crosslink associated with Cpd. The top view of the described structure is shown in FIG. 1A, and the cross sectional cross sectional views of line A-A′ for transistor and line B-B′ for data line are shown in FIG. 1B. A gate line 11 is firstly formed on a substrate 10, wherein the gate line 11 is a straight line without any broken segments in each pixel region, that is the whole gate line is made from the same layer in the same process and without bridging with different layers in different processes. The described structure is then covered by a first insulation layer 12A. Subsequently, a semiconductor layer 13 and an ohmic contact layer 15 are sequentially formed. A metal pattern is then formed to define source/drain electrodes 17A and a data line 17B, wherein the data line 17B is a straight line without any broken segments in each pixel region, that is the whole data line is made from the same layer in the same process and without bridging with different layers in different processes. A second insulation layer 12B is then formed to cover the described structure, and a shielding electrode 18 is formed on the data line 17B to reduce Cpd effect. A third insulation layer 12C is then formed to cover the described structure, and a part of the second and the third insulation layers 12B and 12C are removed to form a via hole A to expose a part of the drain electrode 17A. At last, a pixel electrode 19 is formed on the third insulation layer 12C of the pixel region, and the pixel electrode 19 electrically connects to a part of the drain electrode 17A of the transistor controlling the pixel region through the via hole A.
While the described structure mitigates Cpd effect, deficiencies still exist. Specifically, the described structure increases the overlapping area between the data line 17B and the shielding electrode 18 (so-called common electrode for transmitting a common voltage/signal). Therefore, parasitic RC delay effect is deteriorated due to higher electrical coupling between the data line 17B and the shielding electrode 18.
Accordingly, a novel structure mitigating Cpd effect and reducing parasitic RC between the common line and the data line without drastically increasing costs through requirements for new equipment or change in processes is called for.